hold time check 함수와 setup time check 함수를 이용하여 모델심 시뮬레이션시에 check결과를 내놓는 방법

[Draco]

check 함수 $setup,$hold,$setuphold를 dff안에 내장해서 check하는 예문을 아래와 같이 코딩해보았습니다.

dff의 사용예로 직렬 쉬프터 레지스터를 설계하여 그 동작을 확인해보았습니다.

위와 같은 기능으로 카운터를 설계하여 카운터의 setup time과 hold time을 check하는 회로를 설계하여 보자.

ps)  $setup( data, posedge clk, tSU );
    $hold( posedge clk, data, tHLD );

    $setuphold( posedge clk, data, tSU, tHLD );

    $recrem( posedge clear, posedge clk, tREC, tREM );

    $removal( posedge clear, posedge clk, tREM );
    $recovery( posedge clear, posedge clk, tREC );

    $recovery(negedge bus_control,bus_driver,t_rec)

       $period ( posedge clk,t_limit) //monitor the period of clk within period of clk > limit of t_limit

      $width (posedge clk,t_mpw) // monitor  the minimum pulse width of clk too small

       $skew (clk1,clk2,skew)          // denote the time interval between reference features of 2 waveforms

                                                 // reports a violation when the skew between 2 signals exceeds a specified value

          두 신호간의 경과시간과 지정된 경계값을 벗어 났을 때 오류 발생

 // reports a timing violation if the time interval between an edge-triggered reference event and a data event exceeds a limit

       $nochange (posedge reference_signal,data_signal,start_edge_offset,end_edge_offset)

           // reports an error if a data signal changes value while a reference signal has a specifed value, including an edge transition

      $setup(data, posedge clk &&&(!reset), 3)

  reference: 베릴로그와 함께하는 모델링,합성 그리고 프로토타입


module setup (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam tsetup = 7, delay = 10 ;
(data1 => q) = 10 ;
$setup(data1, posedge data2, tsetup);
endspecify
endmodule

module two_clocks (clk1, clk2, q);
input clk1, clk2;
output q;
specify
  specparam tskew = 7;
  $skew(posedge clk1, posedge clk2, tskew);
endspecify
endmodule

module hold (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam thold = 7, delay = 10 ;
(data1 => q) = 10 ;
$hold(posedge data2, data1, thold);
endspecify
endmodule

module recovery (in1, out1);
input in1 ;
output out1 ;
assign out1 = in1 ? 1'b1 : 1'bz ;
specify
  specparam trecovery = 10;
  $recovery(posedge in1, out1, trecovery);
endspecify
endmodule

module setuphold (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam tsetup = 7,
thold = 7,
delay = 10 ;
(data1 => q) = 10 ;
$setuphold(posedge data2, data1, tsetup, thold);
endspecify
endmodule

module width (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam twidth = 10,
delay = 10 ;
(data2 => q) = 10 ;
$width(posedge data2, twidth);
endspecify
endmodule

module dff (clk, q);
input clk;
output q;
buf (q, clk);
specify
  specparam tperiod = 100 ;
  $period(posedge clk, tperiod);
endspecify
endmodule

module nochange (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);

specify
 specparam tstart = -5,
  tend = 5 ;
  $nochange(posedge data2, data1, tstart, tend);
endspecify

endmodule

`timescale 1ns/100ps
module check_skew
  #(parameter N=4)
  (
    output wire [N-1:0]q,
    input clk_in,rst,
    input [N-1:0] d
    );
   
wire [N-1:0] clk;
assign #0.1 clk[0] = clk_in;
assign #0.3 clk[1] = clk_in;
assign #0.2 clk[2] = clk_in;
assign #0.4 clk[3] = clk_in;

dff U0 (clk[0],rst,d[0],q[0]);
dff U1 (clk[1],rst,d[1],q[1]);
dff U2 (clk[2],rst,d[2],q[2]);
dff U3 (clk[3],rst,d[3],q[3]);

// DFF DUT (q,clk,d);  // vector signals in timing check

//$skew ( posedge clk_in , posedge clk , 0.3 ) ;  // not support skew timing check
wire clk_out;

 two_clocks CLOCK1 (clk_in,clk[1], clk_out);

endmodule

`timescale 1ns/100ps
module two_clocks (clk1, clk2, q);
input clk1, clk2;
output q;
specify
  specparam tskew = 0.1;
  $skew(posedge clk1, posedge clk2, tskew);
endspecify
endmodule

module tb_check_skew;
 reg clk,rst;
 reg [3:0]d;
 wire [3:0]q;
 
 check_skew DUT (.*,.clk_in(~clk));
  initial  forever #10 clk=~clk;
 
 initial
  begin
 #0 rst=1; clk=0;d=4'b1110;
 #100 rst=0;
 //#2.5 d= $random();
 //#10   d= $random();
// @(posedge clk) #2.5  d= $random();
// @(posedge clk) #4  d= $random();
// @(posedge clk) #4  d= $random();
   @(posedge clk) d= $random();
   @(posedge clk) d= $random();
   @(posedge clk) d= $random();
   @(posedge clk) d= $random();
          
  end
endmodule

module check_register
  #(parameter N=4)
  (
    output wire [N-1:0]q,
    input clk,rst,
    input [N-1:0] d
    );
   
wire [N-1:0] n;

dff U0 (clk,rst,d[0],q[0]);
dff U1 (clk,rst,d[1],q[1]);
dff U2 (clk,rst,d[2],q[2]);
dff U3 (clk,rst,d[3],q[3]);

// DFF DUT (q,clk,d);  // vector signals in timing check

endmodule

`timescale 1ns/100ps

module tb_check_register;
 reg clk,rst;
 reg [3:0]d;
 wire [3:0]q;
 
 check_register DUT (.*,.clk(~clk));
  initial  forever #10 clk=~clk;
 
 initial
  begin
 #0 rst=1; clk=0;d=4'b1110;
 #100 rst=0;
 //#2.5 d= $random();
 //#10   d= $random();
// @(posedge clk) #2.5  d= $random();
// @(posedge clk) #4  d= $random();
// @(posedge clk) #4  d= $random();
   @(posedge clk) d= $random();
   @(posedge clk) d= $random();
   @(posedge clk) d= $random();
   @(posedge clk) d= $random();
          
  end
endmodule

`timescale 1ns/100ps
module check_shift
  (
    output wire [3:0]q,
    input clk,rst,d
    );
wire  [3:0] n;   
assign #1 n=  {q[2:0],d};

dff U0 (clk,rst,n[0],q[0]);
dff U1 (clk,rst,n[1],q[1]);
dff U2 (clk,rst,n[2],q[2]);
dff U3 (clk,rst,n[3],q[3]);

endmodule

`timescale 1ns/1ns

module tb_check_shift;
 reg clk,rst,d;
 wire [3:0]q;
 
 check_shift DUT (.*);
  initial  forever #5 clk=~clk;
 
 initial
  begin
 #0 rst=1; d=1'b0;
 clk=1;  // satisfying hold time
 //clk=0;  // not satisfying hold time
 #100 rst=0;
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;  
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
  #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
 
  end
endmodule 

`timescale 1ns/1ns
module check_hold
 (
   input clk,clrn,d,
   output reg q
   );

dff DUT (.*);

endmodule

`timescale 1ns/1ns
module tb_check_hold;
 reg clk,clrn,d;
 wire q;
 
 check_hold U1 (.*);
  initial  forever #5 clk=~clk;
 
 initial
  begin
 #0 clrn=1; d=1'b0;
 // clk=0;  // satisfying hold time
 clk=1;  // violate hold time
 #100 clrn=0;
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;  
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
  #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
 #10 d=1'b1;
 #10 d=1'b0;
 
  end
 
endmodule

`timescale 1ns/1ns
module dff
 (
   input clk,clrn,d,
   output reg q
   );

reg r;

always @(negedge clk or posedge clrn)
 begin
  if(clrn)
   r=0;
  else
   r=#1 d;
 end
always @(posedge clk or posedge clrn)
 begin
  if(clrn)
   q=#1 0;
  else
   q=#1 r;
 end
/*

always @(posedge clk or posedge clrn)
 begin
  if(clrn)
   q=#1 0;
  else
   q=#1 d;
 end
 */
 
specify

(d => q) = 10 ;
$setup(d,posedge clk,2);
$hold (posedge clk,d,3);
$setuphold(d,posedge clk,2,3); 
$recovery(clrn,posedge clk,2);
$removal(posedge clk,clrn,2);
$recrem(posedge clrn,posedge clk,2,3);  // recovery+removal
endspecify

endmodule

`timescale 1ns/1ns
module DFF // IEEE1800
  (
   output reg [7:0] q,
   input clk,
   input [7:0] d
   );

always @(posedge clk)
 q = d;
 
specify  // vector signals in timing check
  $setup (d, posedge clk, 3);
endspecify
endmodule

// verilog online help

Example 1

module setup (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam tsetup = 7, delay = 10 ;
(data1 => q) = 10 ;
$setup(data1, posedge data2, tsetup);
endspecify
endmodule

Example 2

module two_clocks (clk1, clk2, q);
input clk1, clk2;
output q;
specify
  specparam tskew = 7;
  $skew(posedge clk1, posedge clk2, tskew);
endspecify
endmodule

Example 3

module hold (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam thold = 7, delay = 10 ;
(data1 => q) = 10 ;
$hold(posedge data2, data1, thold);
endspecify
endmodule

Example 4

module recovery (in1, out1);
input in1 ;
output out1 ;
assign out1 = in1 ? 1'b1 : 1'bz ;
specify
  specparam trecovery = 10;
  $recovery(posedge in1, out1, trecovery);
endspecify
endmodule

Example 5

module setuphold (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam tsetup = 7,
thold = 7,
delay = 10 ;
(data1 => q) = 10 ;
$setuphold(posedge data2, data1, tsetup, thold);
endspecify
endmodule

Example 6

module width (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam twidth = 10,
delay = 10 ;
(data2 => q) = 10 ;
$width(posedge data2, twidth);
endspecify
endmodule

Example 7

module dff (clk, q);
input clk;
output q;
buf (q, clk);
specify
  specparam tperiod = 100 ;
  $period(posedge clk, tperiod);
endspecify
endmodule

Example 8

module nochange (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam tstart = -5,
tend = 5 ;
$nochange(posedge data2, data1, tstart, tend);
endspecify
endmodule