module TEST(
input clk,rst_n,
input sdsp_on,
input start_n,
input we,cs,
input [5:0] cid,
input [16:0] addr,
output [7:0] out
);
wire [8:0] cnt_out [9:0];
wire we_w[9:0];
generate
genvar i;
for(i=0;i<64;i=i+1)
begin:genI
assign we_w[i]=(we==1'b1)&&(cid==i);
end
endgenerate
cache U0
(
.clk(clk),
.rst_n(rst_n),
/* .sdsp_on(sdsp_on[i]),
.start_n(start_n[i]),
.we(we[i]),
*/
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[0]),
.cs(cs),
// .cid(4'd0),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[0])
);
cache U1
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[1]),
.cs(cs),
// .cid(4'd1),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[1])
);
cache U2
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[2]),
.cs(cs),
// .cid(4'd2),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[2])
);
cache U3
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[3]),
.cs(cs),
// .cid(4'd3),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[3])
);
cache U4
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[4]),
.cs(cs),
// .cid(4'd4),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[4])
);
cache U5
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[5]),
.cs(cs),
// .cid(4'd5),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[5])
);
cache U6
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[6]),
.cs(cs),
// .cid(4'd6),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[6])
);
cache U7
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[7]),
.cs(cs),
// .cid(4'd7),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[7])
);
cache U8
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[8]),
.cs(cs),
// .cid(4'd8),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[8])
);
cache U9
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[9]),
.cs(cs),
// .cid(4'd9),
.addr(addr[12:0]),
.up(),
.cnt_out(cnt_out[9])
);
comparaterBlock U10
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we),
.addr(addr[12:0]),
.cnt(cnt_out),
.out(out)
);
cache R0
(
.clk(clk),
.rst_n(rst_n),
.sdsp_on(sdsp_on),
.start_n(start_n),
.we(we_w[0],
.cs(cs),
// input [7:0] data,
// input color_b, //color r_w,g_w,b_w,black
.addrr(addr),
.up(),
.cnt_out(cnt_out0)
);
endmodule
module cache
(
input clk,rst_n,
input sdsp_on,
input start_n,
input we,cs,
// input [7:0] data,
// input color_b, //color r_w,g_w,b_w,black
input [12:0] addr,
output reg up,
output reg [8:0] cnt_out
);
parameter mType=1'b0; //mode type 0: time series data , 1: position data
// reg cache [2**13-1:0]; //for 1 weight
reg [1:0] cache [2**13-1:0]; // for 0,1,2,3 weights
reg [12:0] cnt;
integer l;
initial
begin
for(l=0;l<1024;l=l+1)
cache[l]=0;
end
reg [1:0] color_intinsity;
always @(*)
begin
if((mType==1'b1)&& data<8'd64)
color_intinsity=2'b00;
else if((mType==1'b1) && data<8'd128)
color_intinsity=2'b01;
else if((mType==1'b1) && data<8'd192)
color_intinsity=2'b10;
else if(data>8'd192)
color_intinsity=2'b11;
else
color_intinsity=2'b00;
end
always @(posedge clk)
begin
if(rst_n==1'b0)
begin
cnt_out<=0;
end
if(start_n==1'b0)
begin
// cnt_out<=0;
end
else if(sdsp_on==1'b1)
begin
if((we==1'b1)&& (cs==1'b1))
begin
if(cache[addr]<3)
if(mType==1'b0)
cache[addr]<=cache[addr]+1'b1;
else
cache[addr]<=color_intensity;
cnt_out<=0;
end
end
// else if((we==1'b0) && (cs==1'b1) && cache[addr]==1'b1)
// cnt_out<=cnt_out+1'b1;
else if((we==1'b0) && (cs==1'b1))
cnt_out<=cnt_out+cache[addr];
end
endmodule
module comparaterBlock
(
input clk,rst_n,
input sdsp_on,
input start_n,
input we,
input [12:0] addr,
input wire [8:0] cnt[9:0],
output wire [7:0] out
);
//wire [8:0] cnt [255:0];
// 媛④퀎: value index瑜④퍡 蹂닿
/* reg [8:0] wcnt0 [0:127];
reg [7:0] widx0 [0:127];
reg [8:0] wcnt1 [0:63];
reg [7:0] widx1 [0:63];
reg [8:0] wcnt2 [0:31];
reg [7:0] widx2 [0:31];
*/
reg [8:0] wcnt3 [0:15];
reg [7:0] widx3 [0:15];
reg [8:0] wcnt4 [0:7];
reg [7:0] widx4 [0:7];
reg [8:0] wcnt5 [0:3];
reg [7:0] widx5 [0:3];
reg [8:0] wcnt6 [0:1];
reg [7:0] widx6 [0:1];
integer k;
reg [8:0] final_val;
reg [7:0] final_idx;
// tie-break: 媛믪씠 媛숈쑝硫 몃뜳좏깮(먰븯硫뺤콉 蹂寃媛
function automatic [17:0] pick2(
input [8:0] a_val,
input [7:0] a_idx,
input [8:0] b_val,
input [7:0] b_idx
);
reg [8:0] o_val;
reg [7:0] o_idx;
begin
if (a_val > b_val) begin
o_val = a_val; o_idx = a_idx;
end else if (b_val > a_val) begin
o_val = b_val; o_idx = b_idx;
end else begin
// equal: lower index wins
if (a_idx <= b_idx) begin
o_val = a_val; o_idx = a_idx;
end else begin
o_val = b_val; o_idx = b_idx;
end
end
pick2 ={o_val,o_idx};
end
endfunction
always @(*) begin
// 256 -> 128
for (k = 0; k < 128; k = k + 1) begin
{wcnt0[k], widx0[k]}=
pick2(cnt[2*k], (2*k),
cnt[2*k+1], (2*k+1));
end
// 128 -> 64
for (k = 0; k < 64; k = k + 1) begin
{wcnt1[k], widx1[k]}=
pick2(wcnt0[2*k], widx0[2*k],
wcnt0[2*k+1], widx0[2*k+1]);
end
// 64 -> 32
for (k = 0; k < 32; k = k + 1) begin
{wcnt2[k], widx2[k])}=
pick2(wcnt1[2*k], widx1[2*k],
wcnt1[2*k+1], widx1[2*k+1]);
end
// 32 -> 16
for (k = 0; k < 16; k = k + 1) begin
{wcnt3[k], widx3[k]}=
pick2(wcnt2[2*k], widx2[2*k],
wcnt2[2*k+1], widx2[2*k+1]);
end
// 16 -> 8
for (k = 0; k < 8; k = k + 1) begin
{wcnt4[k], widx4[k]} =
pick2(wcnt3[2*k], widx3[2*k],
wcnt3[2*k+1], widx3[2*k+1]);
end
// 8 -> 4
for (k = 0; k < 4; k = k + 1) begin
{wcnt5[k],widx5[k]} = pick2(wcnt4[2*k], widx4[2*k],
wcnt4[2*k+1], widx4[2*k+1]);
end
// 4 -> 2
for (k = 0; k < 2; k = k + 1) begin
{wcnt6[k], widx6[k]}=pick2(wcnt5[2*k], widx5[2*k],
wcnt5[2*k+1], widx5[2*k+1]);
end
// 2 -> 1 : 理쒖쥌 몃뜳
// widx6[0], widx6[1] 以理쒕媛믪뿉 묓븯몃뜳ㅻ out쇰줈
/* if(wcnt6[0]<wcnt6[1])
out=widx6[1];
else
out=widx6[0];
*/
begin : FINAL
{final_val, final_idx}= pick2(wcnt6[0], widx6[0],
wcnt6[1], widx6[1]);
end
end
assign out= final_idx;
endmodule