사용자 정합을 64비트로 쓰고 읽기가 가능하도록 변경이 요구됨.
`timescale 1ns/100ps
module uart_tx_fifo64(
input clk,
input rstn,
input [7:0] data_in,
input send,
input read,
output tx,
output busy,
input rx,
output [7:0] data_out,
output valid /* ,
// input s_axis_aresetn;
// input s_axis_aclk;
input s_axis_tvalid,
output s_axis_tready,
input [8:0] s_axis_tdata,
output m_axis_tvalid,
input m_axis_tready,
output [8:0] m_axis_tdata */
);
parameter CLK_FREQ = 200_000_000;
// localparam BAUD_RATE = 115200;
parameter BAUD_RATE = 100_000_000; //100Mbps
// localparam BAUD_RATE = 115200;
parameter HALF_BAUD_RATE = CLK_FREQ / BAUD_RATE /2;
parameter DATA_WIDTH=8;
wire clk_o1,clk_o2;
wire s_axis_aresetn=rstn;
wire s_axis_aclk=clk;
clk_wiz_0 clock
(
.clk_out1(clk_o1), //200MHz
.clk_out2(clk_o2), //500MHz
.clk_out3(clk_o3), //1GHz
.reset(reset),
.locked(locked),
// Clock in ports
.clk_in1(clk)
);
wire clk_o;
assign clk_o = clk_o1;
wire [DATA_WIDTH-1:0] data_In;
wire [2:0] txfifo_count;
wire [2:0] rxfifo_count;
wire txfifo_empty,txfifo_full;
wire rxfifo_empty,rxfifo_full;
wire send_ready, send_valid;
wire [7:0] data_out2;
reg [5:0] send_r;
always @(posedge clk_o)
begin
send_r <= {send_r[4:0],send};
end
fifo_user_write #(.DATA_WIDTH(8),.FIFO_DEPTH(64),.ADDR_WIDTH(6)) TxFifo
(
.clk(clk_o),
.rstn(rstn),
.in_data(data_in),
.in_valid(send),
.in_ready(send_ready),
.user_rd_en(user_rd_en),
.user_rd_data(data_In),
.user_rd_valid(send_valid),
.fifo_empty(txfifo_empty),
.fifo_full(txfifo_full),
.fifo_count(txfifo_count)
);
uart_tx #(.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)) TX
(
.clk(clk_o),
.rstn(rstn),
.data_in(data_In),
.send(send_r[5]),
.tx(tx),
.busy(busy)
);
fifo_user_read #(.DATA_WIDTH(8),.FIFO_DEPTH(64),.ADDR_WIDTH(6)) RxFifo
(
.clk(clk_o),
.rstn(rstn),
.in_data(data_out2),
.in_valid(valid),
.in_ready(rx_ready),
.user_rd_en(read),
.user_rd_data(data_out),
.user_rd_valid(rx_valid),
.fifo_empty(rxfifo_empty),
.fifo_full(rxfifo_full),
.fifo_count(rxfifo_count)
);
uart_rx2
#(
.CLK_FREQ (CLK_FREQ),
.BAUD_RATE (BAUD_RATE)
) RX
(
.clk(clk_o),
.rstn(rstn),
.rx(rx),
.data_out(data_out2),
.valid(valid)
);
/*
axis_data_fifo_v2_0_17_top #(
.C_FAMILY("artix7"),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011),
.C_FIFO_DEPTH(512),
.C_FIFO_MODE(1),
.C_IS_ACLK_ASYNC(0),
.C_SYNCHRONIZER_STAGE(3),
.C_ACLKEN_CONV_MODE(0),
.C_ECC_MODE(0),
.C_FIFO_MEMORY_TYPE("block"),
.C_USE_ADV_FEATURES(825241648),
.C_PROG_EMPTY_THRESH(5),
.C_PROG_FULL_THRESH(11)
) TXfifo (
.s_axis_aresetn(s_axis_aresetn),
.s_axis_aclk(s_axis_aclk),
.s_axis_aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(1'H1),
.s_axis_tkeep(1'H1),
.s_axis_tlast(1'H1),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_aclk(1'H0),
.m_axis_aclken(1'H1),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.almost_empty(),
.prog_empty(),
.almost_full(),
.prog_full(),
.sbiterr(),
.dbiterr(),
.injectsbiterr(1'H0),
.injectdbiterr(1'H0)
);
*/
endmodule
`timescale 1ns/100ps
module tb_uart_tx_fifo512;
parameter CLK_FREQ = 200_000_000;
// localparam BAUD_RATE = 115200;
parameter BAUD_RATE = 100_000_000;
parameter HALF_BAUD_RATE = CLK_FREQ / BAUD_RATE /2;
reg clk;
reg rstn;
reg [7:0] data_in;
reg send;
reg read;
wire tx;
wire busy;
reg rx;
wire [7:0] data_out;
wire valid;
reg s_axis_tvalid;
wire s_axis_tready;
reg [8:0] s_axis_tdata;
wire m_axis_tvalid;
reg m_axis_tready;
wire [8:0] m_axis_tdata;
uart_tx_fifo512 #(.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)) UART
(
.clk(clk),
.rstn(rstn),
.data_in(data_in),
.send(send),
.read(read),
.tx(tx),
.busy(busy),
.rx(rx),
.data_out(data_out),
.valid(valid)
/*
,
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata)
*/
);
assign data_in=s_axis_tdata[7:0];
reg [3:0] delay;
// always @(posedge UART.clk_o)
always @(posedge clk)
begin
{rx,delay}={delay,tx};
end
always #5 clk=~clk;
always @(send)
s_axis_tvalid=send;
initial
begin
clk=1'b0; rstn=1'b1; send=1'b0; read=1'b0;
#600; rstn=1'b0;
#100 rstn=1'b1; s_axis_tdata=8'hA2;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
@(negedge busy);
repeat (100) @(posedge clk);
s_axis_tdata=8'hA1;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
@(negedge busy);
repeat (100) @(posedge clk);
s_axis_tdata=8'hA5;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
@(negedge busy);
repeat (100) @(posedge clk);
s_axis_tdata=8'hA4;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
@(negedge busy);
repeat (100) @(posedge clk);
s_axis_tdata=8'hFF;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
@(negedge busy);
s_axis_tdata=8'hFF;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
@(negedge busy);
s_axis_tdata=8'h0;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
@(negedge busy);
s_axis_tdata=8'h0;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
@(negedge busy);
s_axis_tdata=8'hA1;
repeat (2) @(posedge clk); send=1'b1;
repeat (2) @(posedge clk); send=1'b0;
//@(negedge busy);
/*
s_axis_tdata=8'hA1;
repeat (1) @(posedge clk); send=1'b1;
repeat (1) @(posedge clk); send=1'b0;
@(negedge busy);
*/
READ;
READ;
READ;
READ;
end
task READ;
begin
read=1'b1;
repeat (1) @(posedge clk);
read=1'b0;
repeat (10) @(posedge clk);
end
endtask
endmodule